There are many applications for analog-to-digital converters. Real world analog information must be converted into a digital form before it can be processed by digital devices such as computers.
There are a number of types of analog-to-digital converters employing various conversion methods. Each of these methods offer different performance characteristics and trade offs between operating speed, power consumption, achievable accuracy, chip area, required amplifier gain, bandwidth, impedance matching and noise.
Conventional electronic systems often package analog-to-digital converters (ADCs) on a separate integrated circuit. Generally, increased electronic integration offers a number of advantages. Hence it is desirable to integrate ADCs onto existing integrated circuit chips. This would reduce the total mass, volume, and system power, as well as the number and volume of power supplies in many systems. An indirect benefit would include a lowering of system design time and design error rate.
One example of an application for such integrated analog-to-digital converters is in the field of semiconductor imagers. There have been recent efforts to implement on-chip ADCs onto detector arrays, such as focal-plane arrays (FPAs). Typically, signal chains introduce noise in focal-plane arrays. Therefore, besides the above-described advantages of integrating ADCs, an FPA system with an on-focal-plane (on-chip) ADC would be expected to exhibit superior noise performance. This is due to the inevitable introduction of unwanted noise through cross-talk, clock pickup, power supply noise, electromagnetic interference (EMI) and other mechanisms. Since the serial data rate in the signal chain is typically the highest rate in the entire imaging system, white noise is introduced with a maximum bandwidth. Clock noise and other capacitively-coupled noise sources are also known to increase with increasing data rates.
On-chip ADCs would operate at a significantly lower bandwidth, ameliorating these effects. Since no off-chip analog cabling is required, pick up and vibration sensitivity would also be eliminated. More fundamentally, multiple sampling, or over-sampling, of the detector signal can be more effectively performed on the focal plane as compared to off-chip. Thus, an on-chip ADC would eliminate mechanisms for the introduction of noise, as well as permit increased signal-to-noise ratio through over-sampling techniques. On-focal-plane ADCs can also lead to a reduction in total FPA power dissipation.
Furthermore, digital signals can be digitally processed on-chip as a further level of integration. For example, on-chip digital signal processing can be used for autonomous sensor control, e.g. exposure control, or for control, of windowed region-of-interest readout. Image compression can also be achieved on-chip to reduce off-chip drive requirements.
The incorporation of high resolution ADCs on focal-plane arrays has proved to be a difficult challenge. There is much less silicon area available on focal-plane arrays than on stand-alone ADCs. An ADC with serial architecture would be required to operate with the highest bandwidth of all focal-plane components, since the conversion rate would be the same as the pixel data rate. In a scientific application, a typical pixel data rate is about 100 KHz. In defense applications and in certain scientific applications, data rates in excess of 100 MHZ are often required. The reliability of CMOS at such high data rates circuits is also a concern.
These problems are compounded in scientific applications which routinely require resolutions greater than sixteen bits. This level of resolution generally requires over-sampling techniques that drive the ADC clock rate even higher. On-chip ADCs would also increase focal-plane power dissipation because of the required high speed operation of several analog circuits; compared to the single driver amplifier used in conventional focal-plane readouts. For these reasons, the inventors believe that a serial on-focal-plane ADC architecture would not be optimal.
Another alternative is a massively parallel architecture; for example, with one ADC on each readout pixel in the focal-plane array. However, only a relatively small area is available for most applications; typical pixel size is about 30 .mu.m.sup.2. Thus, this does not leave enough room for conventional ADC approaches which require a relatively larger chip area.
In summary, speed limitations in serial architectures and area limitations in parallel architectures have restricted the implementation of on-focal-plane ADCs. The present inventors have recognized that the use of a semi-parallel architecture can be expected to preserve the advantages, and mitigate the adverse consequences, of both of these architectures. A semi-parallel architecture would, for example, utilize an ADC for every column of the readout. This affords few problems with area in one dimension and tight, but feasible, design space in the other dimension based on the degree of integration of the columns. Such tall, skinny, ADCs would operate, in parallel, on one row of image data at a time.
A number of ADC techniques are available for use in focal-plane applications. These conversion methods differ from each other in terms of operating speed, power consumption, achievable accuracy, and chip area. An important difference between on-focal-plane ADC and a single chip monolithic ADC, is that an on-focal-plane ADC must occupy a relatively small chip area. The real estate becomes an even more serious concern for column-parallel approaches. Due to the unavailability of a large chip area, focal-plane ADCs cannot usually take advantage of elaborate trimming techniques for resolution enhancement. Thus, the immunity of the ADC performance to circuit parameter mismatch is a problem.
Low power operation is preferred in focal-plane ADCs. Maximum overall power dissipation in the combined ADCs would typically be limited to between one and 20 mW. The required resolution and conversion rates vary widely depending upon applications. The conversion rate depends on the array size, the integration time, and the choice of ADC architecture. The rate is usually in the range of 1 KHz to 1 MHz. Scientific infrared imagers usually demand high resolution (greater than sixteen bits), but several other applications require only eight to ten bit accuracy. Thus there is a wide range of operating requirements. Conversion rate requirements vary from 1 kHz to 1 MHz, and the bit resolution requirements vary from six to over sixteen bits. There does not appear to be a single ADC algorithm that optimally meets all of these widely varying requirements.
Candidate ADC algorithms which meet some of these constraints include flash ADCs, successive approximation ADCs, single/dual slope ADCs, and over-sampled delta-sigma ADCs. For ADC operation in the two to ten bit range, the inventors have recognized that the successive approximation ADC is an attractive alternative for focal-plane applications. This kind of ADC achieves high resolution at medium speeds and with minimal power dissipation. One advantage with successive approximation is that for n bits, only n comparisons need to be made. This results in high speed and low power dissipation. Furthermore, this architecture does not require excessive chip area.
The successive-approximation analog-to-digital conversion process is essentially a "ranging" algorithm. Each conversion step estimates the upper and lower bound within which the input voltage lies. The analog voltage is approximated to within a small error by successively shrinking these bounds. The ranging can be done in several ways. One successive-approximation algorithm that is compatible with CMOS implementation is described in S. Ogawa, et al., "A switch-capacitor successive-approximation A/D converter", IEEE Trans. Instrum. and Meas., Vol. 42, pp. 847-853, 1993. One disadvantage with that approach is that the residual voltage decimates to approximately V.sub.ref /2.sup.n after n conversion steps. As a result, the ADC can become susceptible to circuit noise, offset and non-idealities.
It is hence an object of the present invention to overcome these disadvantages in order to realize many of the potential advantages of on-focal-plane ADC. It is also an object of the invention to provide an ADC which requires reduced chip area and power consumption. It is further an object of the invention to provide an ADC with a superior match in DC gain and DC offset, and a minimal ADC error caused by the DC gain. This is done according to the invention by the use of a charge integration successive approximation ADC using a single amplifier. In particular, the invention uses a single charge-integrating amplifier to implement charge balancing.
An initial signal to be digitized is converted to the charge domain using a capacitor. The charge is then transferred to a charge-integrating amplifier circuit. For a differential signal (such as pixel sample and reset outputs) the other side of the input signal is also converted to charge and put on the charge integrating amplifier circuit in the next step. A reference voltage is also converted to charge and divided, e.g., in half, using capacitors and a switch.
Respective storage capacitors are used to hold the resulting charge from the signal and reset levels, respectively. The signal and reset charge values are compared in a comparator and the divided reference charge is transferred to either a signal branch or a reset branch, both of which use a common charge integrating amplifier circuit, depending on which has the lesser signal. The remaining half of the reference charge is divided again. This results in two reference charges, each equal to one-fourth the original value. This process is continued for n bits resulting in n-bits of resolution. Each comparison represents a new bit in the output digital word, starting from the most significant bit. Each time the second branch is selected, a "one" is generated for the digital word.
Since only n comparisons are needed for n bits of resolution, the invention operates at high speed with low power dissipation. It is particularly well suited for focal-plane applications in the 2-10 bit range. In addition, the architecture utilizes a CMOS charge-integrating amplifier, resulting in an ADC well suited for CMOS compatible focal-plane applications. Furthermore, the architecture of the invention requires minimal chip area and is well suited to column-parallel on-chip focal-plane applications.